1. Field of the Invention
The present invention relates to circuitry for performing a built-in self-test (BIST), and in particular, to a BIST method and circuit for generating and verifying a test sequence.
2. Discussion of the Related Art
With the increased complexity and clocking frequencies of integrated circuits, and the use of new technologies down to 32 nm, it is desirable to perform rigorous testing of the data connections between chips and/or input/output terminals of the integrated circuits. An aim of such tests is to ensure that a broad range of signals can be correctly transmitted and received over the data connections.
Built-in self-test (BIST) circuitry is a type of automatic test equipment for rigorously testing data connections between chips, and is integrated with the functional circuitry of the chip. The BIST circuitry generally comprises two main elements: a pseudo-random bit sequence (PRBS) generator, which generates a pseudo-random bit sequence to be used as a test sequence that is transmitted over the data connection during a testing phase; and verification circuitry, which checks that the test sequence is correctly received at the receive side.
A problem with existing BIST circuitry is that it can be relatively costly in terms of chip area. One of the reasons is that a PRBS generator is often provided at both the transmission and receive side. Furthermore, existing BIST circuitry generally does not allow flexibility in the stress applied by the test sequence. The stress is defined by the sequence length, and determines the maximum number of “0” or “1” bits that are generated by the PRBS generator in a row.